Since the netlist has already been placed and routed at later stages, it is generally undesirable to resynthesize the netlist to implement the new logic function because otherwise that is virtually equivalent to starting everything from scratch and much development time is needed. By applying a psmallatch on the post-APR netlist to create the ECOed netlist that fulfills the new logic specification instead, the cost needed to implement the new logic can be much reduced.
Both pre-mask ECO and post-mask ECO require changing the logic function of the circuit design. They are different in the way that what and how the additional logic is implemented. In pre-mask ECO, there is usually no hard constraint regarding the available resources. In post-mask ECO, however, only spare cells reserved for ECO purposes can be used because the netlist layout has already been fixed in the metal level. Not only are the types of spare cells limited, but the number of available spare cells is also strictly constrained.
EasyECOis a tool for Performing Engineering Change Orders, making Functional ECO really easy!
Easy-Logic's EasyECO is an award-wining tool for performing engineering change orders. The core algorithms won the champion in IEEE/ACM International Conference on Computer-Aided Design (ICCAD) CAD Contest 2012, 2013, and 2014, which is one of the most significant conference in electronic design automation. EasyECO has been widely tested in the industry. It has been proven that EasyECO can produce patches whose sizes are only 1% of what manual ECO or existing traditional ECO tools could achieve, and in a much shorter time.
EasyECO can carry out both pre-mask and post-mask ECO.
Compared with traditional ECO tools, EasyECO’s innovative ECO procedure shortens ECO time much; EasyECO can be faster up to several ten times than traditional tools.
EasyECO supports advanced technology process (<10nm). Commonly used circuit design techniques such as using multibit-registers and multiple power domains are well supported.
1. Painless
Intuitive preparation
Push-button execution
2. Fast
Save days or weeks of manual ECO
Can be much faster than other ECO tools
3. Powerful
Support for ECO that are very complex to be done manually
Support for physical constraints
4. Accurate
Just add the smallest amout of patch logic, and just ntroduce the smallest amount of changes
Smaller patch logic usually means easier timing closure
5. Robust
Support for any feature size
Support for various technology libraries
Support for cross power domains
Support for cross clock domains
Support for ECO in almost all stages in the design flow
Support for design of unlimited size
Support for patch of unlimited size
EasyECO can complete functional ECO system with all required functions.
1. Design input
Gate level netlists (Verilog)
Standard cell libraries (Liberty)
Synthesis log (SVF, VSDC)
Physical constraints (SDC, DEF)
2. Automatic ECO
Support for changes about module interface, module addition/removal, register addition/removal, logic transformation, and other kinds of ECO
Automatic patch generation
Automatic technology mapping
Layout-aware
3. Spare cells
Support for gate-array cells
Support for spare cell instances
Support for spare modules
4. Special cell types
Support for multi-bit registers
Support for power isolation cells
Support for clock gating cells
5. Design for test
MBIST cells are kept intact
Scan chains are preserved
Scan chain can be generated during ECO
6. ECO results
Optimimally mapped ECOed netlist
Scripts for third-party ECO tools
64-bit Linux workstation (Centos 6/7, ArchLinux, RedHat, SUSE, Ubuntu)
of minimum kernel version 2.6
Minimum of 16GB of RAM
Minimum of 50GB of free disk space
Multi-core decent CPU
Easy-Logic Services and Supports:
Easy-Logic application engineers can answer your technical questions via various means, including but not limited to, email, instant message, or video conference
On-site and off-site technical assistance and custom training are available
For more information, please email us: info@easylogic.hk